High data reliability, high speed of memory access, lower power consumption and reduced chip size are features that are demanded from semiconductor memory. In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by stacking dice vertically and interconnecting the dice using through-silicon vias (TSVs). Benefits of the 3D memory devices include shorter interconnects which reduce circuit delays and power consumption, a large number of vertical vias between layers which allow wide bandwidth buses between functional blocks in different layers, and a considerably smaller footprint. Thus, the 3D memory devices contribute to higher memory access speed, lower power consumption and chip size reduction. Example 3D memory devices include Hybrid Memory Cube (HMC) and High Bandwidth Memory (HBM).
For example, High Bandwidth Memory (HBM) is a type of memory including a high-performance random access memory (DRAM) interface and vertically stacked DRAM. A typical HBM stack of four DRAM dice has two 128-bit channels per die for a total of eight input/output channels and a width of 1024 bits in total. An interface (I/F) die of the HBM provides an interface with the eight input/output channels, which function independently of each other. For example, a clock frequency, a command sequence, and data can be independently provided for each channel. Thus, the eight input/output channels are not necessarily synchronous to each other.
There are several types of tests which may be performed for HBM. For example, a test pad may be included on the I/F die in order to perform a probe test. In the probe set, input/output lines of a channel may be tested. A number of channels to be tested at a time in the probe test are limited to one under various constraints, such as a size of the test pad and issues in an internal circuit and its wirings. The various constraints also include factors regarding a tester and a probe card for controlling the test pad from outside of the I/F die. Another type of test can be performed using a memory Built-In Self Test (mBIST) circuit that may be provided on the I/F die. The mBIST circuit is provided for verifying failures resulting from stacking the die. A specification of the HBM provides a definition of operations for the mBIST circuit. The mBIST circuit may include an algorithmic pattern generator (APG) and a comparator. Using the mBIST circuit, input/output lines of one channel may be tested. The number of channels tested at a time may be limited to one because the APG occupies a relatively large area on the I/F die with a limited footprint, and including multiple APGs on the I/F die is impractical.
The HBM includes a plurality of data buses and their respective channels that can operate individually. Interference between the respective channels, which may be caused by noises or the like when the respective channels individually operate, may be an issue. FIG. 1 is a wiring diagram of native input/output lines (IOs) between an interface (I/F) die and a core die of the HBM in a semiconductor device. As shown in FIG. 1, noise on one channel (e.g., Core 1 channel) may affect operations of other channels (e.g., Core 0 channel, Core 2 channel, etc.). Thus, testing the plurality of channels individually operating may be desirable in order to address the interference between the respective channels. However, as described above, a number of channels tested by the probe test with the test pad or tested with the mBIST circuit have typically been limited to one.